The present invention relates to a circuit for comparing a digital value having CMOS voltage levels with a digital value having ECL (xe2x80x9cEmitter-Coupled Logicxe2x80x9d) voltage levels.
CMOS and ECL signals are not compatible. Indeed, CMOS signals practically vary between 0 and the supply voltage to define the two logic states, while ECL signals vary between the supply voltage and a value slightly smaller (about 0.3 volt) than the supply voltage, to define the two logic states.
FIG. 1 shows an example of a circuit where it is necessary to compare ECL signals with CMOS signals. This circuit is a phase-locked loop including a controlled oscillator 10 of high frequency. To operate at high frequencies, circuits in ECL technology are often used.
However, circuits made in ECL technology have a relatively high static current consumption and, thereby, this technology is used only for the portions of a circuit that must operate at high frequency. The other circuits are thus made in CMOS technology. Such a case occurs, for example, in the phase-locked loop of FIG. 1 for a low-pass filter 12 that controls oscillator 10 and a phase comparator 14, the output of which is provided to filter 12.
Phase comparator 14 receives a signal at a reference frequency Fref and the signal provided by oscillator 10 via a frequency divider 16. The dividing ratio of divider 16 is of course sufficiently high to bring the frequency of oscillator 10 down to a value compatible with the CMOS technology, and thus exploitable by phase comparator 14.
A conventional example of a frequency divider 16 is shown in FIG. 1. This divider includes a counter 18 rated by the output signal of oscillator 10. A digital comparator 20 compares the content D of counter 18 with a programmable value N and resets counter 18 when its content D reaches value N. Assuming that the output of divider 16 is reset signal RST of counter 18, a frequency division by N is obtained.
Counter 18 and comparator 20 must be able to operate at the frequency of oscillator 10. They are for this purpose made in ECL technology. However, programming signal N is provided by circuits that do not have to operate at high frequency and it is thus provided by CMOS circuits.
The problem raised thus is to compare a digital value N having CMOS levels with a digital value D having ECL levels.
FIG. 2 shows a solution to compare such signals. In this example, it is assumed that signal N includes two bits N0 and N1, while signal D includes two bits D0 and D1. Each of the bits of signal N is provided to a circuit 22 for converting a CMOS level into an ECL level, the output of which is provided to a first input of an XNOR gate 24 in ECL technology. The corresponding bits of ECL signal D are respectively provided to the second inputs of XNOR gates 24. An AND gate 26 receives the outputs of XNOR gates 24 and provides a logic value 1 when digital values N and D are equal.
In the general case, there are as many converters 22 and XNOR gates 24 as there are bits of values N and D to be compared, AND gate 26 having a corresponding number of inputs.
A disadvantage of this solution is that it requires a high number of elementary ECL gates, each of which adds a static current consumption.
This problem is also encountered in circuits made in CML (xe2x80x9cCurrent-Mode Logicxe2x80x9d) technology.
An object of the present invention is to provide a comparator of ECL or CML signals with CMOS signals having a particularly low static current consumption.
To achieve this object, an embodiment of the present invention provides a comparator of a first digital value of n bits having CMOS voltage levels with a second digital value of n bits having ECL or CML voltage levels, including a decoder in CMOS technology provided to provide 2n CMOS signals, each of which corresponds to a different product of n bits, each of the n bits being a respective bit of the first digital value or its complement; 2n AND gates in ECL or CML technology respectively associated with the 2n CMOS signals, connected to implement an OR function of 2n ECL or CML signals, each of which corresponds to a different product of n bits taken from among the bits of the second value or their complements, according to the same choice as for the product of n bits of the respective CMOS signal; and means for deactivating the AND gates associated with the CMOS signals having a value of 0.
According to an embodiment of the present invention, the comparator includes 2n switches respectively controlled by the CMOS signals and each of which is arranged between a differential stage of a respective AND gate and a common biasing current source.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.